Integrated Memristive-based Circuits for Spatially Distributed Computing and Applications
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1) cellular neural networks with memristor templates for abnormal cardiac wavefront detection and 2) decision trees with memristor boundaries for network intrusion detection. The first application aims to provide a computing solution for future next generation cardiac implants. A model of the distributed cellular neural network for wavefront detection is proposed. After training, the networks achieve very high >99% specificity, >96% accuracy, >93% sensitivity, and >92% precision for detecting abnormal wavefronts and wave brakes in cardiac signals recorded in human tissue. The preliminary results and future plans for its memristor based implementation will also be discussed. The proposed distributed hardware implementation is based on a fabric of chiplets where each chiplet processes information from itself and four neighbors. The chiplet would consist of a pre-processing analog front end for filtering and amplification of sensor signal, a Hilbert transform block to obtain phase information, and the cellular processing core to identify abnormal cardiac wavefronts and the actuator for therapy. This research aims to open the path for future research and development of an integrated heart-conformal system with high-resolution sensing, high-performance computing, and low-energy actuation, capable of millisecond response time and painless therapy of life-threatening fibrillation. The second application in this dissertation is related to network intrusion detection via a spatially-distributed decision tree using memristor-based chiplet leaves. Each chiplet receives an input, compares it to a predefined boundary stored in the memristor and provides a binary decision output to select one of the interconnected leaves on the lower level. The memristor-based circuit for one decision tree leaf consists of circuitry for memristor read and programming, operational amplifiers for signal amplification, a compensation and a comparator block. By comparison with prior work, our proposed design is optimized for area and speed which are performance metrics needed for real-time network monitoring. Both these applications rely on the local data exchange between chiplet units, for their respective architectures. Each chiplet will be tested independently, keeping only the chiplets with 100% yield of working memristors to assemble the network. The network can be assembled after the memristive devices are programmed for each chiplet unit. Moreover, this approach allows a variety of network architectures to be experimentally explored after the chiplets are taped-out. The simulation results and tape-out designs will be discussed as well as plans for chip measurements and prototyping. This distributed, tile-based approach offers practical advantages when designing systems that require modularity and adaptability. Since each chiplet operates as an independent unit with dedicated circuit block memristor-based comparators, amplifiers, and decision logic, the same hardware can be reused or reconfigured for different applications by simply adjusting the programmed thresholds or changing how the chiplets are interconnected. This makes the architecture especially useful for edge computing tasks where localized decision-making is critical. For instance, the same fundamental building blocks could be adapted for pattern recognition in biomedical signals or environmental monitoring. Additionally, because chiplets are tested individually and assembled post-fabrication, the approach improves overall system yield and allows experimental flexibility, including the ability to explore multiple network configurations using the same set of fabricated tiles.
Emerging non-volatile memory device technologies, such as memristors, are being investigated to enable new ways of computing particularly in energy-constrained environments for edge applications. Memristors can perform as synaptic devices with programmable resistance offering learning and memory capabilities in intelligent computing systems. While their applicability for sizable deep neural networks potentially mappable to dedicated hardware accelerator chips has been investigated, challenges with the yield, manufacturability, and non-idealities issues in large arrays of devices have prevented large scale adoption. In the traditional approach of using a single large chip, prototyping is limited to the population of devices available which might include a large percentage of manufacturing defects.This doctoral work designs and tests novel chiplets and related circuit blocks based on emerging synaptic electronic devices, such as memristors, for spatially-distributed network architectures. Two applications are explored, namely cellular neural networks for cardiac implants and decision trees for network intrusion detection. Both these applications rely on local data exchange between individually tested chiplet units. The experimental challenges and application opportunities for these and similarly tiled architectures are being investigated. This proposed approach provides robustness against the typical memristor yield and manufacturability issues, enables the reuse of chiplets and circuit designs and maps well to distributed architectures with 2-3 orders of magnitude improvement in speed and energy efficiency as needed for edge computing. Furthermore, the modularized design of each block allows for high reusability across different applications. The functional units such as low-pass filter, operational amplifiers, programmable memristive blocks, are designed as reusable building blocks, which can be configured for a wide range of spatially distributed computing tasks. To understand the opportunities and challenges of this approach, two applications benefiting from emerging spatially distributed computing technologies are explored in this work
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