Electronic Thesis/Dissertation
 

All Optical Fast Fourier Transform On Chip with Heating Tunability Design, Simulation, Fabrication, and Performance Analysis

Open Access

This thesis explores fundamentals of optical computing by means of fast Fourier transform Integration on Silicon On Insulator chip technology toward its implementation in analog and temporal domain. This is done by cascading (N-2) stages of delayed interferometers (couplers and phase shifters) where a parallel set of N time samples are taken and using the delay lines and phase of the optical components (constructive/deconstructive interference) the DFT is computed. Hence it is important to understand the behavior and the quality of the Optical Fast Fourier Transform (OFFT) and its sensitivity due to the important role of phase, time delay, and power to overcome the system of delayed interferometers to become unstable. This was done by analyzing the characteristics of the extinction ratio of the OFFT as a function of the phase, time delay, and power. The OFFT design was built on passive components (2 x 2 couplers : cascaded Mach Zehnder Inteferometer) used for addition and subtraction through optical interference, waveguides with short path differences are used for phase shifting and waveguides with long path differences are used for signal delay based on the needed number of outputs. While in principal an OFFT network could be created with perfect phase alignment, in practice active phase calibration at a specific temperature is required to compensate for fabrication variance. This phase calibration was accomplished with a heating element placed along on one of the waveguide paths of the cascaded interferometers. Since the OFFT is a system of imbalanced interferometers, there are additional bends designed to compensate for the difference in power ratios of the arms.Alongside the fabrication and sensitivity analysis of the OFFT, its individual components such as grating coupler, 2 x 2 (star) coupler, y branch, straight, and spiral waveguides and their characteristics were studied. The individuals’ contribution to loss and power consumption of the entire system was incorporated to the on chip performance analysis.

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