A 400 MHZ ∑Δ ADC FOR BAND-PASS IF DIGITIZATION AROUND 100 MHZ WITH EXCESS LOOP DELAY COMPENSATION
Open AccessThe past few years has seen a tremendous amount of work being published in the area of continuous-time sigma-delta ADC designs with various compensation techniques to counter its susceptibility to non-idealities like clock jitter and excess loop delay, to name a few.The focus of this thesis is the design of a tunable continuous time band-pass sigma-delta modulator that utilizes a novel excess loop delay compensation technique proposed by M. Ortmanns et al. to optimize the SNR of the modulator, besides preserving its stability by incorporating a full clock cycle delay.An improved, low noise, compact gyrator-C structure is proposed to obtain a high-Q band-pass filter subsequently used in the design of a second-order band-pass sigma-delta modulator clocked at 400 MHz for direct conversion of narrow band signals at 100 MHz. The proposed structure eliminates the need of a capacitor bank/array for the coarse tuning of the modulator since this structure enables coarse tuning in the range of 80 to 120 MHz and fine tuning of 5 MHz above or below the centre frequency. This modulator has been implemented in CMOS AMI 0.5µ process and achieves an SNDR of 46 dB, calculated from post-layout simulations. The power consumption of this design is 49 mW at a supply of 3V.
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