Machine Learning Enabled Design Framework for High-performance, Energy-efficient, Fault-tolerant, and Secure On-chip Communication
Open AccessThe proliferation of multicore architectures has pushed for a paradigm shift from computation-centric to communication-centric systems. In modern multicore systems, Network-on-Chips (NoCs) have emerged as the standard interconnect fabrics for processing cores, cache banks, and memory controllers on the chip. With aggressive scaling of transistor technology to lower dimensions, NoC architectures are facing several urgent challenges, namely scaling performance, minimizing power consumption, and providing reliable and secured communications. However, simultaneously addressing these problems is difficult due to the explosion of the design space and the complexity of handling many trade-offs.In this dissertation, we introduce an intelligent design framework for NoC with architectural innovations and machine learning algorithms. The goal of the proposed architecture is to auto-tune NoC functionality in order to simultaneously maximize performance, energy-efficiency, reliability, and security. In this dissertation, a number of NoC architectural designs are proposed to improve NoC performance, power, reliability, and security independently. Furthermore, machine learning algorithms, such as reinforcement learning (RL) and neural networks, are used to automatically compute decisions that optimize NoC functionality based on runtime data from application execution (communication workload, memory access, traffic patterns, etc.), architecture (buffer utilization, network congestion, router/link failures, delays, etc.), and current operating conditions (voltage and current levels, temperature, heat, etc.). In this thesis, we investigate different techniques and machine learning algorithms with increased complexity and expanded design space, as summarized in the following research tasks. First, we explore the trade-offs between the fault-tolerant capability and the overheads of different error detection and correction techniques. We propose a proactive NoC design to optimize fault-tolerance and performance with reinforcement learning (RL). First, we propose a new proactive error handling technique comprised of a dynamic scheme for enabling per-router error detection/correction hardware and an effective retransmission mechanism. Second, we propose the use of RL to train the dynamic control policy with the goals of providing increased fault-tolerance and reduced latency. The proposed design allows routers to switch among several fault-tolerant operations with the aim of maximizing NoC reliability and performance.Second, we simultaneously tackle the three major challenges faced by NoC designs, namely improving performance, reducing power consumption, and enhancing reliability. We propose an intelligent NoC design framework, named IntelliNoC, which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques, namely multi-function adaptive channels to improve energy-efficiency, an adaptive error detection/correction and retransmission control to enhance reliability, and a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead.Third, we further enhance NoC reliability against permanent faults and transient errors. We propose CURE, a deep reinforcement learning (DRL)-based NoC design framework that simultaneously reduces network latency, improves energy-efficiency, and tolerates transient errors and permanent faults. First, in CURE, we extend the key innovation, multi-function adaptive channels, in IntelliNoC by adding reversibility to the channels. The new reversible multi-function channel (RMC) provides flexibility for improving reliability at the link level via retransmission buffers and reversing the propagation direction to avoid faulty links. The RMC also enhances performance by allowing the NoC to dynamically adapt to traffic because it provides extra link bandwidth in a specific direction at high network loads. Second, we propose a new NoC circuitry design that can handle permanent faults in routers and links. Specifically, we modify the circuitry of the router to mitigate transient and permanent faults that occur in the routing pipeline stages. We also re-design the control logic of the bypass links in IntelliNoC to handle permanent link failures. Further, for the complex dynamic interactions of these techniques, we propose using deep-Q-learning (DQL) to train a proactive control policy to provide improved fault-tolerance, reduced power consumption, and improved performance with reduced overheads.Lastly, we tackle the security problem of NoCs. In NoCs, maliciously implanted Hardware Trojans (HTs) inject faults into on-chip communications that saturate the network, resulting in the leakage of sensitive data via side channels and significant performance degradation. While existing techniques protect NoCs by detecting and isolating HT-infected components, they inevitably incur occasional inaccurate detection with considerable network latency and power overheads. We propose TSA-NoC, a learning-based design framework for secure and efficient on-chip communication. The proposed TSA-NoC uses an artificial neural network (ANN) for runtime HT-detection with higher accuracy. Furthermore, we propose a deep reinforcement learning (DRL)-based adaptive routing design for HT mitigation with the aim of minimizing network latency and maximizing energy-efficiency.
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