An Efficient Cache Coherence Mechanism for Chip Multiprocessors
Open AccessDue to power and clocking constraints, integrating more processing cores onto a single chip, instead of increasing the frequency has become the norm in modern processor design. This design choice has resulted in the advent of multicore architectures also referred to as Chip Multiprocessors (CMPs) as the dominant processor architecture.CMPs introduce many challenges that need to be addressed if we are to harness their potential performance. One such challenge comes with shared-memory processor architectures, which namely is the cache coherence problem. The trend of putting more and more cores inside a single chip makes efficient cache coherence design imperative to get performance scaling out of CMPs. Earliercache coherence research targeted the multi-processor systems. CMPs have different technological parameters and physical constraints than earlier multi-processor systems, which require a fresh look at the design of cache coherence protocols. Optimizing on-chip resource utilization is crucial for CMPs, as for example a remote but on-chip cache-to-cache access is far less costly than an off-chip access. This is different than earlier multiprocessors where shared resources were always off-chip. On-chip scalable point-to-pointinterconnects are also emerging for CMPs. With the utilization of suchinterconnects, relative distance between cores varies a lot in CMPs compared to the traditional multi-processor systems. These topological and technological differences call for a cache coherence protocol design, which maximizes on-chip communication with the purpose of reducing off-chip data transfers.Contemporary architectures employ write-invalidate based cache coherence protocols that are known to generate coherence misses that later produce additional latency. This is especially true under producer-consumer sharing patterns and can become a performance bottleneck as the number of cores increases. On the other hand, write-update based cache coherence protocols can solve the coherence misses problem, but they tend to generate excessive network traffic. Previous studies have shown that a single protocol approach is not sufficient for many sharing patterns.As a solution, this dissertation presents two mechanisms to design efficient and scalable cache coherence protocols for CMPs. First, we propose an adaptive hybrid, invalidate/update, protocol to reduce coherence misses observed in write-invalidate based protocols. The proposed protocol is based on a write-invalidate scheme, however, adaptively it pushes updates to potential consumers based on the observed producer-consumer sharing patterns. Secondly, we extend this adaptive protocol with interconnection resource aware mechanisms. These mechanisms require modest hardware extensions in order to benefit from such adaptive protocols. In addition, the proposed mechanisms can be implemented on top of any write-invalidate protocol and can work with existing language, compiler, and processor designs.Extensive analytical as well as experimental evaluations, conducted on a tiled-CMP via full-system simulator, were used to assess the performance from our proposed dynamic hybrid protocols. Performance studies used a set of scientific applications from SPLASH-2 and NAS parallel benchmarking suites. The experimental results, confirmed by the analytical model, have shown that the proposed mechanisms reduce cache-to-cache sharing misses up to 48% and in return speed up application performance up to 25%. In addition, the proposed interconnection-resource-aware mechanism is proven to perform well under varying interconnection loads.
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