A Residue Arithmetic Nanophotonic Computer
Open Access DepositedThe current Complementary Metal-Oxide-Semiconductor (CMOS) technology faces significant challenges as the end of Moore's Law approaches. Moreover, power density no longer stays constant as it was initially thought by Dennard’s scaling. At the same time, the data movement challenge exacerbates system performance bottlenecks. These combined limitations, as such, highlight the need for innovative approaches beyond traditional technology and architectures. Optical computing techniques are among the promising solutions because of their rapid readout, energy efficiency, and high-bandwidth characteristics. The residue number system (RNS) is of particular interest because it decomposes numbers into smaller independent digits that can be processed in parallel. Furthermore, RNS and nanophotonics have a natural affinity, where most operations can be achieved while routing using electro-optical switches, giving rise to an innovative Processing-in-Network (PIN) paradigm. Given the aforementioned benefits and the synergy between nanophotonic switches and the representation of the residue number system, we introduce innovative efficient architectures that can achieve high computational speed per watt. In this work, we first explore efficient electro-optical residue adders based on multistage interconnection networks, which are fundamental for many other operations, and demonstrate that arbitrary size Benes networks are superior to existing works. Based on that, we further extend this adder to multipliers, converters, sign detection units, and polynomial evaluation. Using these fundamental circuits serve as building blocks, we explore and demonstrate how more complex architectures based on RNS can be designed. Among the critical applications work considered, we investigate how this technology accelerates machine learning tasks in deep neural networks (DNNs) and devise end-to-end designs using nanophotonic residue techniques. To this end, RNS was shown to reduce the complexity of the optical circuits and lower power requirements as it shortens the critical path of the system. By leveraging wavelength division multiplexing, the proposed accelerators were shown to achieve data-level parallelism, further improving hardware utilization and overall performance. Thus, our approach was shown to result in developing efficient machine learning accelerators. In addition, the work capitalizes on RNS PIN concepts to create architectural support for collective operations. This architecture establishes a photonic network at the chip level to accelerate communication, computation, and synchronization among many-core systems. Moreover, its processing-in-network capability allows computations to be executed during data transmission, which minimizes overhead. We experimentally evaluated our work against cutting-edge solutions. The results demonstrated that the proposed RNS-based nanophotonic architectures achieved significant speedup along with a notable decrease in energy consumption. As such, these novel photonic residue architectures were found to open a new chapter in computing.
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