CMOS-Compatible Artificial Synaptic Devices for Neuro-inspired Computing
Open Access DepositedAbstractEmerging synaptic devices are needed as key building blocks for next-generation neuro-inspired computing hardware to meet the demand of low power consumption and data intensive operations. The interest in different synaptic device technologies, such as two-terminal resistive switches and three-terminal ferroelectric transistors, has seen a rapid rise in the past decade due to their electronic programmability, non-volatile state storage with years long retention and in-memory computing capabilities. Because they offer an efficient mapping of vector-matrix multiplication and other matrix operations, these devices offer complementary functionality with traditional transistor-based (CMOS) digital hardware. However, prototyping a neural network system with these devices is not an easy task given their issues related to manufacturability, reliability and yield, metrics which need to be characterized across a large device population. Moreover, the efficient device metrology and full system integration requires to have these devices monolithically integrated onto CMOS circuitry, e.g., to provide the converters, decoders, and current limiting transistors to control and program the synaptic matrices. In addition, realistic models of these devices need to be promptly developed to obtain estimates of how these device arrays would perform in hardware neural networks and what their potential accuracy performance would be. This work aims to develop data-driven methods to support device fabrication, integration, and modeling efforts for resistive switches and ferroelectric transistors. The focus is particularly on two-terminal titanium oxide-based resistive switches, their advantages and drawbacks as synaptic devices for neuro-inspired computing hardware. The applicability and expansion of this work to three-terminal synaptic devices, namely hafnium oxide—based ferroelectric transistors (FeFETs) and electrochemical devices (ECRAM) are also investigated. The results for the design, fabrication, and heterogeneous integration of 20,000 resistive switches on foundry CMOS are presented. The challenges of optimizing single device performance and translating those results to a large device propagation using in-house fabrication techniques are discussed, particularly for two-terminal resistive switching devices. Optimal device behavior assumes a planar substate surface. For this work, the CMOS chips come from the foundry pre-planarized. Another consideration is that device scaling has been shown to increase performance, but it requires electron beam lithography which can be challenging on CMOS circuitry due to charging effects due to the thick oxide layer on top. Characterization using Design of Experiments approach is described to gain an understanding on how to identify the best operating conditions for peak yield and the switching performance across the array of two-terminal resistive switches. Insights into how this integration and characterization methodology could be translated for three-terminal devices in other future projects are included. In parallel, this work explores how to utilize device measurement data to develop realistic device models for neural network simulations. Several data-driven device modeling approaches using 1-D and multivariate Kriging interpolation as well as heteroscedastic gaussian process interpolation of these resistive switches and ferroelectric FET devices have been proposed. The validity of these multi-dimensional approaches is benchmarked against the conventional binning interpolation method using statistical methods on synthetic datasets with known distributions and on experimental datasets. Our results show a superior performance in extracting the mean and standard deviation profiles from non-ideal device data. This work will contribute integrated synaptic arrays and multi-dimensional device models towards future investigations of hardware neural network training and prototyping.
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